The present invention relates generally to class AB operational amplifiers, and more particularly to a class AB operational amplifier having a split folded-cascode structure.
In a typical xe2x80x9cfolded meshxe2x80x9d type of class AB amplifier structure, bias current in the output transistors is not well-controlled, especially when the structure is used in circuit designs that are not low-power, low voltage designs.
The article xe2x80x9cCompact Low-Voltage Power-Efficient Operational Amplifier Cells for VLSIxe2x80x9d by De Langen and Huijsing, (IEEE JSSC volume 33, No. 10, October 1988) describes a rail-to-rail operational amplifier including a class AB output stage having xe2x80x9cfolded meshxe2x80x9d feedback control circuitry. xe2x80x9cPrior Artxe2x80x9d FIG. 1 herein is taken from the foregoing article and shows a simplified schematic diagram for the described operational amplifier in which a circuit branch connected to the drain of the current mirror transistor M10 is xe2x80x9csplitxe2x80x9d into above folded mesh circuitry, which includes transistors M13-16. (A conventional folded cascode structure would eliminate transistors M13 and M16.) The folded mesh circuitry produces differential output signals, one of which drives the gates of output transistor M1 and a corresponding output current sensing transistor M11. The other one of the differential output signals drives the gates of output transistor M2 and a corresponding current sensing transistor M12, which is used to provide class AB control feedback. The current in output transistor M1 is sensed by transistor M11 to provide a corresponding input signal to the class AB control circuit, and the current in output transistor M2 is sensed by transistor M12 to provide a corresponding input signal to the class AB control circuit.
The resulting output voltage VAB produced by the class AB control circuit is applied as a feedback loop control signal to the gate of cascode transistor M16. The voltage VAB is compared to the gate voltage of transistor M14, which is developed across transistor M18 by the flow of reference current I18 through diode-connected transistor M18. The quiescent output current through output transistors M1 and M2 is a design parameter that can be controlled by the choice of the value of reference current I18, the ratio of the channel-width-to-channel-length of current sensing transistor M11 to that of output transistor M1, and the ratio of the channel-width-to-channel-length of current sensing transistor 12 to that of output transistor M2.
The circuitry of prior art FIG. 1 works very well with low values of the supply voltage VDD, e.g. 2 volts. However, in situations in which a higher value of VDD is required, e.g. 5 volts, the circuit of FIG. 1 tends to produce inadequate control of the quiescent bias current through the output transistors M1 and M2. The inadequate bias current control is due to the fact that the differential class AB drive voltage signals produced by the folded mesh circuitry and applied to the gates of output transistors M1 and M2 can differ by as much as 3 volts at larger values of VDD. The folded mesh circuitry and class AB control a loop in of FIG. 1 is quite sensitive to VDD. For VDD equal to approximately 2 volts, the quiescent bias current in the output transistors is fairly controllable, but if VDD is increased to approximately 5 volts, the quiescent bias current in the output stage will increase substantially, which results in substantially increased power consumption of the operational amplifier. The undesirable increase in the quiescent output bias current through output transistors M1 and M2 occurs because the difference between their gate voltages increase as the supply voltage VDD increases. In order to achieve precise control of the quiescent output bias current, the class AB control loop needs to the attenuate the foregoing gate voltage difference, which is referred to as the xe2x80x9csystematic errorxe2x80x9d. Unfortunately, the class AB loop gain for the circuit of FIG. 1 is relatively low. If the properties of the folded mesh cascode circuit structure including transistors M13-16 is examined, it can be seen that only the common mode signals in the folded mesh circuitry obtain the same benefit as the main amplifier signals from the cascode circuit. However the class AB control loop structure presents a differential feedback signal in the folded mesh circuitry, and each pair of cascode transistors is source-coupled and consequently loses the main benefit of using cascode transistors. The resulting lower impedance in the class AB control loop in turn results in a lower class AB loop gain, and this results in a reduced ability to the attenuate the above-mentioned systematic errors. The gain of the class AB control loop is poor, which causes poor control of, and consequently instability of, the quiescent bias current flowing through output transistors M1 and M2.
Thus, there is an unmet need for a class AB output stage that provides a highly controllable quiescent bias current in the output transistors at relatively high power supply voltages and at relatively low power supply voltages.
There also is an unmet need for a class AB output stage that provides a highly controllable quiescent bias current in the output transistors over a fairly broad range from relatively low power supply voltages to relatively high power supply voltages with no additional cost or complexity compared to that of a typical prior art folded mesh type of class AB output stage circuit.
There also is an unmet need for a class AB control feedback loop that more effectively attenuates a reduces the systematic error associated with the folded mesh circuitry of the closest prior art in order to accomplish accurate control of the quiescent bias current flowing through the output transistors of a class AB output stage.
Accordingly, it is an object of the present invention to provide a class AB output stage that provides a highly controllable quiescent bias current in the output transistors at relatively high power supply voltages and at relatively low power supply voltages.
It is another object of the present mentioned to provide a class AB output stage that provides a highly controllable quiescent bias current in the output transistors over a fairly broad range from relatively low power supply voltages to relatively high power supply voltages with no additional cost or complexity compared to that of a typical prior art folded mesh type of class AB output stage circuit.
It is another object of the present invention to provide a class AB control feedback loop that more effectively attenuates (reduces) the systematic error associated with the folded mesh circuitry of the closest prior art in order to accomplish accurate control of the quiescent bias current flowing through the output transistors of a class AB output stage.
Briefly described, and in accordance with one embodiment, the present invention provides circuitry for controlling quiescent bias current in output transistors of a class AB output stage is controlled by providing substantially equal amounts of differential amplification to both an output of a differential input stage (2) of an amplifier and an output (17,18) of a class AB control circuit (46) of the amplifier. A split input transistor circuit structure for a first side of the differential input stage (2) includes first (15) and second (16) input transistors with gates coupled to a first input (Vin+) of the amplifier. A third input transistor (10) of the input stage has a gate coupled to a second input (Vinxe2x88x92) of the amplifier. A split folded cascode circuit structure having a common gate configuration includes first (25) and second (30) cascode transistors having their gates coupled to a reference voltage and their drains coupled to the first (26) and second (37) gate drive conductors, respectively, and a third cascode transistor (22) has a gate connected to the reference voltage and a source coupled to a drain of the third input transistor.
In the described embodiments, a pull-up transistor (40) in the first class AB output stage (46) has a gate coupled to a first gate drive conductor (26) and a drain coupled to a first output conductor (42) and a pull-down transistor (41) in the first class AB output stage (46) having a gate coupled to a second gate drive conductor (37) and a drain coupled to the first output conductor (42). The bias current in the output transistors is sensed and compared with a reference current (53) by means of the class AB control circuit (46) to produce a differential error signal which is amplified to produce a differential error current signal which applied to the source of one of the first (25) and second (30) cascode transistors. In the described embodiments, the differential error signal is amplified to produce a differential error current signal which is introduced into the sources of the first and second gate-coupled cascode transistors. The common-gate cascode circuit structure and the error current signal applied to the sources of the first and second gate-coupled cascode transistors causes the drains of the first (25) and second (30) cascode transistors to present high output impedances to the first (26) and second (37) gate drive conductors, which results in high loop gain and consequently results in precise control of a first quiescent bias current in the first (40) and second (41) output transistors.
In the described embodiments, third (32) and forth (35) cascode transistors each has a gate coupled to another reference signal conductor (34), the third and fourth cascode transistors having drains coupled to the first (26) and second (37) gate drive conductors, respectively, and sources coupled to first (33) and second (36) current source devices, respectively. In the described embodiments, the first (15), second (16) and third (10) input transistors and the first output transistor (40) are P-channel transistors, and the second output transistor (41), the first (25) and second (30) cascode transistors, the first (27) and second (29) current source transistors, and the first current mirror control transistor (24) are N-channel transistors.
In the described embodiments, the first class AB control circuitry (46) includes differential amplifier circuitry including first (54), second (55) and third (56) source-coupled transistors, a reference current source (53), and a diode-connected reference voltage transistor (58) having a drain connected to receive a reference current from the reference current source, the first and second inputs of the first class AB control circuitry being connected to gates of the first (54) and second (55) source-coupled transistors, respectively, a gate of the third source-coupled transistor (56) being coupled to a gate of the diode-connected reference voltage transistor (58), a drain of the third source-coupled transistor (56) being coupled to the first conductor (17), and drains of the first (54) and second (55) source-coupled transistors being coupled to the first conductor (18).
In one embodiment, the differential input stage includes a fourth input transistor (11) having a source, a gate, and a drain connected to the source, gate, and a drain, respectively, of the third input transistor (10). The amplifier includes a second class AB output stage (4A) including a third output transistor (40A) having a gate coupled to a third gate drive conductor (26A) and a drain coupled to a second output conductor (42A) and a fourth output transistor (41A) having a gate coupled to a fourth gate drive conductor (37A) and a drain coupled to the second output conductor (42A). The operational amplifier also includes a second split folded cascode stage which is similar to the first split folded cascode stage and second class AB control circuitry which is similar to the first class AB control circuitry. The drains of third (25A) and fourth (30A) cascode transistors in the second split folded cascode stage present high output impedances to the third (26A) and fourth (37A) gate drive conductors resulting in high loop gain and consequently resulting in precise control of a quiescent bias current in third (40A) and fourth (41A) output transistors. A common mode feedback circuit (62) has a first input connected to the first output conductor (42), first and second outputs connected to the first (17) and second (18) conductors, respectively, to establish a common mode component on the first output conductor (42), a second input connected to the second output conductor (42A), and third and fourth outputs connected to third (17A) and fourth (18A) conductors, respectively, to establish the common mode component on the second output conductor (42A).